1. Field of the Invention
The present invention relates to memory devices. More specifically, matching a clock signal delay to a delay through a memory array.
2. Background
Memory devices typically contain a memory array having a series of memory cells arranged in rows and columns. Additional control circuitry is connected to the memory array to control the storage of the information in the memory array as well as retrieval of information from the array. Each row of memory cells in the memory array has an associated word line. Each column of memory cells in the memory array has an associated bit line. A particular memory cell within the array is selected by activating the corresponding word line and bit line. The memory cell data is provided on the bit line to a sense amplifier which amplifies the signal and provides the data output.
A clock signal is used to activate the sense amplifier. The sense amplifier cannot be activated by the clock signal until the data from the memory cell is available at the sense amplifier input. If the sense amplifier is activated too early, invalid data may be received by the sense amplifier and provided at the output. When a particular word line is activated, a signal must propagate across the word line to the selected memory cell. Another time period is required to activate the memory cell itself and copy the memory cell data onto the bit line. Therefore, the clock signal to activate the sense amplifiers must be delayed while the word line signal propagates across the word line and data is provided on the bit line.
FIG. 1 illustrates a block diagram of a conventional memory device having a row decoder 12 and a column decoder 14, each of which receive a memory address on address line 10. Row decoder 12 selects a particular word line within a memory array 16 based on the memory address provided. Similarly, column decoder 14 selects a particular column within memory array 16 based on the memory address provided. A plurality of sense amplifiers 18 are connected to the column decoder and receive the data from the selected memory cell.
FIG. 2 illustrates a prior art circuit capable of delaying a clock signal prior to activating the sense amplifiers. Memory array 16 includes a series of word lines 20 arranged in rows and a series of bit lines 22 arranged in columns. Memory cells 24 are arranged in rows and columns within memory array 16. Sense amplifiers 18 are connected to bit lines 22 and provide amplified outputs 30. A delay simulation circuit 28 receives a clock signal on an input line 26 and generates a sense amplifier clock signal for activating sense amplifiers 18. The delay provided by simulation circuit 28 represents the worst case delay of a signal propagated through memory array 16. This delay assumes that a word line signal propagates across memory array 16 to the last possible bit line (BL.sub.n), thereby representing the longest delay across the memory array. The delay circuit also includes a worst case delay for providing the memory cell data to the bit line and the propagation delay of the data to the sense amplifier. An additional delay is encountered as the clock signal is propagated from delay simulation circuit 28 to the appropriate sense amplifier 18. Delay simulation circuit 28 generally includes an additional delay to provide an extra time period to ensure that sense amplifiers 18 are not activated before the memory cell data is available. Thus, the circuit illustrated in FIG. 2 delays activation of the sense amplifiers for more than a worst case time period, thereby reducing the overall speed and efficiency of the memory device.
As shown in FIG. 2, the word line signal propagates from left to right. In contrast, the sense amplifier clock signal propagates from right to left. Therefore, in a worst case situation, a worst case delay is provided by delay simulation circuit 28 and an additional delay is provided by the propagation from circuit 28 to the leftmost sense amplifier 18. In this case, the data from memory cell 24 is available at the leftmost sense amplifier 18 for a significant period of time before the sense amplifier clock signal is received.
Further illustrated by FIG. 2, existing clock delay circuits are located within the memory device, but outside memory array 16. When designing memory devices, the area used by the memory array is minimized to reduce the chances of contaminants entering the array and rendering the memory device defective. Furthermore, new memory devices are continuously being designed to provide a greater amount of memory capacity in a single device. Designers attempt to provide a maximum number of individual memory cells within a particular memory array. Thus, the memory array is a "sacred" portion of the memory device, and is under continuous improvement to provide maximum storage capacity in a minimum memory array area. As a result, delay circuits such as circuit 28 in FIG. 2 are placed outside the memory array portion of the memory device.